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NXP Semiconductors /LPC11E6x /SCT0 /DMAREQ1

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Interpret as DMAREQ1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DEV_10RESERVED0 (DRL1)DRL1 0 (DRQ1)DRQ1

Description

SCT DMA request 1 register

Fields

DEV_1

If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,…, event 5 = bit 5).
RESERVED

Reserved
DRL1

A 1 in this bit makes the SCT set DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers.
DRQ1

This read-only bit indicates the state of DMA Request 1.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data